Speaker
Description
The WEST thermal fusion reactor is currently an upgraded evaluation environment for the diagnostics to-be-deployed in the constructed ITER tokamak. In particular, fast metallic impurities diagnostics is tested, that in future can increase reaction efficiency and provide safe mode of operation with the divertor. A diagnostic system has been provided in the framework of the collaboration and the optimization of the processing within this instrument is ongoing. This is to reduce the latencies as far as possible in order to provide a feedback loop to the tokamak control systems. The heterogeneous diagnostic system implements an FPGA front-end and server back-end architecture, where computational workloads are decomposed into these devices.
Although the operational device has already been constructed with an FPGA front- end and server back-end, there is still an ongoing study how to augment and further optimize the back-end for new online diagnostic workloads.
This work discusses the tests of selected hardware accelerators on the back-end server PC side, in particular, the PCIe cards and CPUs. Their feasibility for the application in the WEST is evaluated and assessed. The bottlenecks of implementations are discussed and the issues of provision of runtime processing are presented. The relevant hardware limitations are pinpointed. The performance results of the runs of the optimized algorithms with the accelerators are shown. This is to both maximize the throughput of data processing from a multichannel, multipixel GEM detector for the calculation of spatial distribution of impurities in the running experiment in the reactor.
